Chip manufacturers stand to boost output and lower unit costs as Samsung and TSMC commit to ASML’s highest‑resolution lithography and to a shift from six‑inch to 12‑inch photomasks. The combined equipment and mask changes are aimed at improving yields on the most advanced processors and memory, a move that could relieve capacity pressure across the supply chain.
ASML’s High NA extreme ultraviolet lithography, already in limited use at Intel on its 18A node for select Core Ultra Series 3 Panther Lake processors, will be adopted by Samsung and TSMC on staggered timetables. Samsung plans to use the High NA systems for DRAM production by 2028. TSMC says it will bring the technology into its advanced node roadmap beginning in 2030. ASML also reported that Intel has produced more than one million wafers with the new process.
The three companies announced a parallel initiative to move mask production from the current six‑inch standard to a larger 12‑inch format. TSMC highlighted the operational benefits, saying the larger masks will "increase fab productivity, lower chipmaking costs and remove stitching constraints." By printing finer NA EUV features across a bigger stencil, fabs can avoid the stitching steps that now add complexity and expense for very large dies.
ASML set out a development timeline for the larger masks, with initial testing of 12‑inch photomask fabs projected to begin in 2031 and volume production expected in 2033. SK Hynix is evaluating whether to join the consortium, expanding the list of major manufacturers engaged in the transition.
Industry observers note the path from laboratory adoption to high‑volume manufacturing can be slow and difficult. Intel’s experience with High NA shows initial deployments can scale, but bringing throughput and yields to mass production levels requires time, new process integration and supply‑chain coordination. Those same challenges could push back the schedules Samsung and TSMC announced.
For now, the plan sets clear milestones: Samsung’s DRAM move in 2028, TSMC’s node roll‑out in 2030, mask testing in 2031 and mask production in 2033. If the timeline holds, fabs using High NA tools and 12‑inch masks would print larger, stitch‑free features more efficiently, lowering per‑chip costs and easing pressure on capacity for high‑end chips and memory.
